View LTM4639-15_8346305.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 for more information www.linear.com/ltm4639 low v in 20a dc/dc module step-down regulator typical application description the lt m ? 4639 is a complete 20 a output high efficiency switch mode step-down dc/dc module (micromodule) regulator. included in the package are the switching controller, power fets, inductor and compensation components. operating over an input voltage range from 2.375v to 7 v, the ltm4639 supports an output voltage range of 0.6 v to 5.5 v, set by a single external resistor. only a few input and output capacitors are needed. current mode operation allows precision current sharing of up to four ltm4639 regulators to obtain up to 80 a output. high switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. the device supports frequency synchronization, multiphase / current sharing, burst mode operation and output voltage tracking for supply rail sequencing. a diode-connected pnp transistor is included for use as an internal temperature monitor. for up to 20 v input operation, please see the ltm4637. the ltm4639 is offered in a 15mm 15mm 4.92mm bga package. the ltm4639 is rohs compliant. l, lt , lt c , lt m , polyphase, burst mode, module, linear technology, the linear logo are registered trademarks and ltpowercad is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611, 6677210, 8163643. 3.3v in , 1.5v out , 20a dc/dc module ? regulator features applications n complete 20a switch mode power supply n 2.375v to 7v input voltage range (v in < 4.5v, need c pwr bias) n 0.6v to 5.5v output voltage range n 1.5% maximum total dc output voltage error (C40c to 125c) n differential remote sense amplifier for precision regulation (v out 3.3v) n current mode control/fast transient response n parallel multiphase current sharing (up to 80a) n frequency synchronization n selectable pulse-skipping or burst mode ? operation n soft-start/voltage tracking n up to 88% efficiency (3.3v in , 1.5v out ) n overcurrent foldback protection n output overvoltage protection n internal temperature monitor n overtemperature protection n 15mm 15mm 4.92mm bga package n telecom servers and networking equipment n industrial equipment n medical systems n high ambient temperature systems n 3.3v input systems 3.3v to 1.5v efficiency and power loss pgood v out v out_lcl diff_out v osns + v osns ? v fb ltm4639 5k r fb ** 40.2k 100k 22f 6.3v 4 v in 3.3v 0.1f 4639 ta01a v in compa compb track/ss run f set mode_pllin temp ? temp + intv cc extv cc sgnd gnd ot_test c pwr * see table 5 ** see table 1 2.2f 1f +5v bias c compa 180pf 100f* 6.3v 2 680f* 2.5v 2 v out 1.5v 20a + c ff * 180pf c bot * 22pf output current (a) 0 70 efficiency (%) power loss 80 85 90 100 4639 ta01b 75 95 0 1.0 1.5 2.0 2.5 3.0 3.5 4.5 0.5 4.0 18 20 1412 16 6 108 2 4 efficiency power loss c pwr = 5v freq = 400khz ltm4639 4639f
2 for more information www.linear.com/ltm4639 pin configuration absolute maximum ratings v in , c pwr , ot _ test .................................. C 0.3 v to 10 v v out _ lcl , pgood , extv cc .......................... C0. 3 v to 6v mode _ pllin , f set , track / ss , v osns C , v osns + , diff _ out ................... C0. 3 v to intv cc v fb , compa , compb ( note 7) ................. C 0.3 v to 2.7 v run ( note 5) ............................................... C0. 3 v to 5v intv cc peak output current ( note 6) .................. 10 0 ma internal operating temperature range ( note 2) .................................................. C 40 c to 125 c storage temperature range .................. C 55 c to 125 c maximum peak body reflow temperature ........... 24 5 c (note 1) electrical characteristics symbol parameter conditions min typ max units v in range input dc voltage range v in < 4.5v, c pwr bias l 2.375 7 v c pwr voltage 4.5 5 6 v v out range output dc voltage range l 0.6 5.5 v v out(dc) output voltage, total variation with line and load c in = 22f 3, c pwr = 5v c out = 100f ceramic, 470f poscap r fb = 40.2k, mode_pllin = gnd v in = 2.375v to 7v, i out = 0a to 20a (note 4) l 1.477 1.50 1.523 v the l denotes the specifications which apply over the specified internal operating temperature range (note 2), otherwise specifications are at t a = 25c. v in = 3.3v, c pwr = 5v, per the typical application in figure 22. order information bga package 133-lead (15mm 15mm 4.92mm) v in 1 2 3 4 5 6 7 8 109 11 12 b c d e f g h j k l a m intv cc f set compa track/ss mode_pllin intv cc top view sgnd v out v in gnd temp + temp ? extv cc v fb pgood pgood c pwr ot_test run v osns + diff_out v out_lcl v osns ? compb t j(max) = 125c, ja = 9.5c/w, jcbottom = 4c/w, jctop = 6.7c/w, jb = 4.5c/w ja derived from 95mm 76mm pcb with 4 layers; weight = 2.8g values determined per jesd51-12 part number pad or ball finish part marking* package type msl ra ting temperature range (see note 2) device finish code ltm4639ey#pbf sac305 (rohs) ltm4639y e1 bga 4 C40c to 125c ltm4639iy#pbf ltm4639y ltm4639iy snpb (63/37) ltm4639y e0 bga 4 C40c to 125c ? consult marketing for parts specified with wider operating temperature ranges. *pad or ball finish code is per ipc/jedec j-std-609. ? terminal finish part marking: www.linear.com/leadfree ? recommended lga and bga pcb assembly and manufacturing procedures: www.linear.com/umodule/pcbassembly ? lga and bga package and t ray drawings: www.linear.com/packaging ltm4639 4639f
3 for more information www.linear.com/ltm4639 the l denotes the specifications which apply over the specified internal operating temperature range (note 2), otherwise specifications are at t a = 25c. v in = 3.3v, c pwr = 5v, per the typical application in figure 22. electrical characteristics symbol parameter conditions min typ max units input specifications v run run pin on threshold v run rising 1.1 1.25 1.4 v v runhys run pin on hysteresis 130 mv i q(vin) input supply bias current v in = 7v , v out = 1.5v , burst mode operation, i out = 0.1a v in = 7v , v out = 1.5v , pulse-skipping mode, i out = 0.1a v in = 7v , v out = 1.5v , switching continuous, i out = 0.1a shutdown, run = 0, v in = c pwr = 7v 25 35 68 45 ma ma ma a i s(vin) input supply current v in = 3.3v, v out = 1.5v, i out = 20a, c pwr = 5v v in = 7v, v out = 1.5v, i out = 20a, c pwr = 5v 10.35 4.93 a a i pwr (in) control power current 3.3v in to 1.5v out at 0a load, c pwr = 5v 28 ma output specifications i out(dc) output continuous current range v in = 3.3v, v out = 1.5v (note 4) 0 20 a ?v out (line) v out line regulation accuracy v out = 1.5v, v in from 2.375v to 7v, c pwr = 5v, i out = 0a l 0.02 0.04 %/v ?v out (load) v out load regulation accuracy v out = 1.5v, i out = 0a to 20a, v in = 3.3v, c pwr = 5v (note 4) l 0.1 0.3 % v out(ac) output ripple voltage i out = 0a, c out = 100f ceramic, 470f poscap v in = 3.3v, v out = 1.5v, c pwr = 5v 20 mv p-p ?v out(start) turn-on overshoot c out = 100f ceramic, 470f poscap, v out = 1.5v, i out = 0a, v in = 3.3v, c pwr = 5v 15 mv t start turn-on time c out = 100f ceramic, 470f poscap, no load, track/ss = 0.001f, v in = 3.3v, c pwr = 5v 0.6 ms ?v outls peak deviation for dynamic load load: 5a to 12.5a load step, 1s rise time c out = 100f 2 ceramic, c out 2 poscap, v in = 3.3v, v out = 1.5v, c pwr = 5v 30 mv t settle settling time for dynamic load step load: 5a to 12.5a load step, 3.3v, v in = 5v, v out = 1.5v c out = 100f 2 ceramic, 680f poscap 30 s i outpk output current limit v in = 3.3v, v out = 1.5v v in = 7v, v out = 1.5v 30 30 a a control section v fb voltage at v fb pin i out = 0a, v out = 1.5v l 0.594 0.60 0.606 v i fb current at v fb pin (note 7) C12 C25 na v ovl feedback overvoltage lockout l 0.65 0.67 0.69 v i track/ss track pin soft-start pull- up current track/ss = 0v 1.0 1.2 1.4 a t on(min) minimum on-time (note 3) 100 ns r fbhi resistor between v out_lcl and v fb pins 60.05 60.40 60.75 k remote sense amplifier v osns + , v osns C cm range common mode input range v in = 3.3v, run > 1.4v, c pwr = 5v 0 3.6 v v diff_out(max) maximum diff_out voltage i diff_out = 300a intv cc C 1.4 v v os input offset voltage v osns + = v diff_out = 1.5v, i diff_out = 100a 2.5 mv ltm4639 4639f
4 for more information www.linear.com/ltm4639 the l denotes the specifications which apply over the specified internal operating temperature range (note 2), otherwise specifications are at t a = 25c. v in = 3.3v, c pwr = 5v, per the typical application in figure 22. symbol parameter conditions min typ max units a v differential gain (note 7) 1 v/v sr slew rate (note 6) 2 v/s gbp gain bandwidth product (note 6) 3 mhz cmrr common mode rejection (note 7) 60 db i diff_out diff_out current sourcing 2 ma psrr power supply rejection ratio 5v < v in < 7v (note 7) c pwr tracking v in 100 db r in input resistance v osns + to gnd 80 k pgood output v pgood pgood trip level v fb with respect to set output v fb ramping negative v fb ramping positive C10 10 % % v pgl pgood voltage low i pgood = 2ma 0.1 0.3 v intv cc linear regulator v intvcc source output 5v < v in < 7v, c pwr tracking v in 4.8 5 5.2 v v ldoint intv cc load regulation i cc = 0 to 40ma, c pwr = 5.5v 2 % v extvcc external v cc switchover extv cc ramping positive, c pwr = 5.5v, intv cc output 5v l 4.5 4.7 v v ldoext extv cc voltage drop i cc = 25ma, v extvcc = 5v, c pwr = 5.5v 75 220 mv oscillator and phase-locked loop f sync frequency sync capture range mode_pllin clock duty cycle = 50% 250 800 khz f nom nominal frequency v fset = 1.2v 450 500 550 khz f low lowest frequency v fset = 0v 210 250 290 khz f high highest frequency v fset 2.4v 700 770 850 khz i freq frequency set current 9 10 11 a r mode_pllin mode_pllin input resistance 250 k v ih_mode_pllin clock input level high 2.0 v v il_mode_pllin clock input level low 0.8 v temperature diode v temp temp diode voltage i temp = 100a 0.6 v tc v temp temperature coefficient l C2 mv/c electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltm4639 is tested under pulsed load conditions such that t j t a . the ltm4639e is guaranteed to meet performance specifications over the 0c to 125c internal operating temperature range. specifications over the full C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltm4639i is guaranteed to meet specifications over the full C40c to 125c internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3: the minimum on-time condition is specified for a peak-to-peak inductor ripple current of ~40% of i max load. (see the applications information section) note 4: see output current derating curves for different v in , v out and t a . note 5: limit current into the run pin to less than 2ma. note 6: guaranteed by design. note 7: 100% tested at wafer level. ltm4639 4639f
5 for more information www.linear.com/ltm4639 typical performance characteristics 7v efficiency graph 2.5v to 1v with 7.5a/s load step, c pwr = 5v 2.5v to 1.2v with 7.5a/s load step, c pwr = 5v 2.5v to 1.5v with 7.5a/s load step, c pwr = 5v 3.3v to 1v with 7.5a/s load step, c pwr = 5v 3.3v to 1.2v with 7.5a/s load step, c pwr = 5v 2.5v input efficiency graph 3.3v efficiency graph 5v efficiency graph output current (a) 0 70 efficiency (%) 80 85 90 100 2 10 14 4637 g01 75 95 8 18 20 4 6 12 16 2.5v to 1.8v 2.5v to 1.5v 2.5v to 1.2v 2.5v to 1v c pwr = 5v freq = 350khz output current (a) 0 70 efficiency (%) 80 85 90 100 2 10 14 4639 g02 75 95 8 18 20 4 6 12 16 3.3v to 2.5v 3.3v to 1.8v 3.3v to 1.5v 3.3v to 1.2v 3.3v to 1v c pwr = 5v freq = 400khz output current (a) 0 70 efficiency (%) 80 85 90 100 2 10 14 4639 g03 75 95 8 18 20 4 6 12 16 5v to 3.3v 5v to 2.5v 5v to 1.8v 5v to 1.5v 5v to 1.2v 5v to 1v c pwr = v in freq = 500khz output current (a) 0 70 efficiency (%) 80 85 90 100 2 10 14 4639 g03 75 95 8 18 20 4 6 12 16 7v to 5v 7v to 3.3v 7v to 2.5v 7v to 1.8v 7v to 1.5v 7v to 1.2v 7v to 1v c pwr = v in freq = 550khz 50s/div compa connected to compb c ff = 180pf, c bot = 22pf, c compa = 180pf c out = 100f cer 2, 680f 2.5v 6m poscap 2 load step 0a to 7.5a v out v p-p = 80mv 4639 g05 50s/div compa connected to compb c ff = 180pf, c bot = 22pf, c compa = 180pf c out = 100f cer 2, 680f 2.5v 6m poscap 2 v out v p-p = 80mv 4639 g06 load step 0a to 7.5a 50s/div compa connected to compb c ff = 180pf, c bot = 22pf, c compa = 180pf c out = 100f cer 2, 680f 2.5v 6m poscap 2 v out v p-p = 80mv 4639 g07 load step 0a to 7.5a 50s/div compa connected to compb c ff = 180pf, c bot = 22pf, c compa = 180pf c out = 100f cer 2, 680f 2.5v 6m poscap 2 v out v p-p = 80mv 4639 g08 load step 0a to 7.5a 50s/div compa connected to compb c ff = 180pf, c bot = 22pf, c compa = 180pf c out = 100f cer 2, 680f 2.5v 6m poscap 2 v out v p-p = 80mv 4639 g09 load step 0a to 7.5a ltm4639 4639f
6 for more information www.linear.com/ltm4639 typical performance characteristics 3.3v to 1.5v with 7.5a/s load step, c pwr = 5v 5v to 1.8v with 7.5a/s load step, c pwr = 5v 5v to 3.3v with 7.5a/s load step, c pwr = 5v 7v to 5v with 7.5a/s load step, c pwr = 5v 50s/div compa connected to compb c ff = 180pf, c bot = 22pf, c compa = 180pf c out = 100f cer 2, 680f 2.5v 6m poscap 2 v out v p-p = 80mv 4639 g10 load step 0a to 7.5a 50s/div compa connected to compb c ff = 180pf, c bot = 22pf, c compa = 180pf c out = 100f cer 2, 680f 2.5v 6m poscap 2 v out v p-p = 80mv 4639 g11 load step 0a to 7.5a 50s/div compa connected to compb c ff = none, c bot = 22pf, c compa = 180pf c out = 47f cer 1, 220f 6.3v 15m poscap 2 v out v p-p = 250mv 4639 g12 load step 0a to 7.5a 50s/div compa connected to compb c ff = none, c bot = 22pf, c compa = 180pf c out = 22f cer 1, 150f 6.3v 15m poscap 2 v out v p-p = 400mv 4639 g13 load step 0a to 7.5a turn-on no load start-up pre-biased load recycling v in (on-off-on) output short-circuit output ripple noise 20ms/div run 1v/div v out 0.5v/div v in = 5v v out = 1v i out = 20a sw 4639 g14 20ms/div run 2v/div v out 0.5v/div v in = 5v v out = 1v, v out = 0.5v bias i out = 20a sw 4639 g15 1s/div run 2v/div v out 0.5v/div v in = 5v v out = 1v sw 4639 g16 500s/div v out 0.5v/div i in 200ma/div v in = 5v v out = 1v sw 4639 g17 1s/div v in = 3.3v v out = 1v i out = 20a 4639 g18 v p-p = 8mv ltm4639 4639f
7 for more information www.linear.com/ltm4639 pin functions v in ( a1-a6, b1-b6, c1-c6): power input pins. apply input voltage between these and gnd pins. recommend placing input decoupling capacitance directly between v in and gnd pins. v out ( j1-j10, k1-k11, l1-l11, m1-m11): power output pins. apply output load between these and gnd pins. recommend placing output decoupling capacitance between these pins and gnd pins. review table 5. output range 0.6v to 5.5v. gnd ( c7, c9, d1-d6, d8, e1-e5, e7, e9, f1-f5, f7-f9, g1-g9, h1-h9): power ground pins for both input and output. pgood ( f 11, g 12): output voltage power good indicator. open-drain logic output is pulled to ground when the output voltage exceeds a 10% regulation window. both pins are tied together internally. sgnd ( g 11, h 11, h 12): signal ground pin. return ground path for all analog and low power circuitry. tie a single connection to the output capacitor gnd. see layout guidelines in figure 21. temp + (f6): temperature monitor. see applications in- formation section. temp C (e6): kelvin return of the internal temperature monitor. mode_ pllin ( a 8): forced continuous mode, burst mode operation, or pulse- skipping mode selection pin and external synchronization input to phase detector pin. connect this pin to intv cc to enable pulse- skipping mode. connect to ground to enable forced continuous mode. floating this pin will enable burst mode operation. a clock on this pin will enable synchronization with forced continuous operation. see the applications information section. c pwr (b7): control bias input. required to operate the ltm4639 regulator below 4.5 v input. for v in 4.5 v up to 7v connect c pwr to v in . to maintain soft-start function, sequence v in before c pwr , then enable the run pin. if the run pin has a pull-up resistor to v in , then sequence c pwr after v in . ot_test (b9) : used for test purposes. float this pin, or tie to v in to disable overtemperature protection. f set (b12): a resistor can be applied from this pin to ground to set the operating frequency, or a dc voltage can be applied to set the frequency. see the applications information section. track/ss (a9): output voltage tracking pin and soft- start inputs. the pin has a 1.2 a pull-up current source. a capacitor from this pin to ground will set a soft-start ramp rate. in tracking, the regulator output can be tracked to a different voltage. see the applications information section. v fb (f12): the negative input of the error amplifier. internally, this pin is connected to v out_ lcl with a 60.4k precision resistor. different output voltages can be programmed with an additional resistor between v fb and ground pins. in polyphase ? operation, tying the v fb pins together allows for parallel operation. see the applications information section. comp a ( a 11): current control threshold and error amplifier compensation point. the current comparator threshold increases with this control voltage. tie all comp pins together for parallel operation. this pin can be compensated externally for optimized loop response or connected to the compb pin. see the applications information section. compb ( a 12): default compensation network corresponding to table 5. tie this pin to compa to use default compensation. see the applications information section. run (a10): run control pin. a voltage above 1.4 v will turn on the module. a 5.1 v zener diode to ground is internal to the module for limiting the voltage on the run pin to 5v and allowing the use of a pull - up resistor to v in for enabling the device. limit current into the run pin to 2ma. int v cc (a7, d9): internal 5 v ldo for driving the control circuitry and the power mosfet drivers. both pins are internally connected. the 5 v ldo has a 100 ma current limit. intv cc is controlled and enabled when run is activated high. see applications section. this pin is an output, do not drive this pin. package row and column labeling m ay vary among module products. review each package layout carefully. ltm4639 4639f
8 for more information www.linear.com/ltm4639 pin functions extv cc (e12): external power input to an internal control switch allows an external source greater than 4.7v , but less than 6 v to supply ic power and bypass the internal intv cc ldo. extv cc must be less than v in at all times during power-on and power-off sequences. see the applications information section. 5 v output application can connect the 5v output to this pin to improve efficiency. the 5 v output is connected to extv cc in the 5 v derating curves. v out_lcl (l12): this pin connects to v out through a 1m resistor, and to v fb with a 60.4 k resistor. the remote sense amplifier output diff_out is connected to v out_lcl , and drives the 60.4 k top feedback resistor in remote sensing applications. when the remote sense amplifier is used, diff_out effectively eliminates the 1 m from v out to v out_lcl . when the remote sense amplifier is not used, then connect v out_lcl to v out directly. v osns + (j12): (+) input to the remote sense amplifier. this pin connects to the output remote sense point. the remote sense amplifier can be used for v out 3.3v. connect to ground when not used. v osns C (m12): (C) input to the remote sense amplifier. this pin connects to the ground remote sense point. the remote sense amplifier can be used for v out 3.3v. connect to ground when not used. diff_out (k12): output of the remote sense amplifier. this pin connects to the v out_lcl pin for remote sense applications. otherwise float when not used. the remote sense amplifier can be used for v out 3.3v. mtp1, mtp2, mtp3, mtp4, mtp5, mtp6, mtp 7, ( a12, b 11, c 10, c 11, c 12, d 10, d 11, d 12): extra mounting pads used for increased solder integrity strength. leave floating. ltm4639 4639f
9 for more information www.linear.com/ltm4639 block diagram figure 1. simplified ltm 4639 block diagram power control c v out v in 5.1v 1m 60.4k f set run v fb sgnd compa v out_lcl r2 r1 mode_pllin track/ss r fset 75k r fb 90.9k 47pf c soft-start 4639 f01 0.3h m1 v out c pwr v out 1v 20a v in +5v bias v in 2.375v to 7v m2 internal comp 2.2 sgnd internal loop filter compb intv cc 2.2f 250k diff_out v osns + v osns ? gnd pgood intv cc extv cc > 1.4v = on < 1.1v = off max = 5v ? ? + + 1.5f 35v 10f 6.3v + c in c out + temp + temp ? ot_test 10k 400mv 499k ptc intv cc diff amp + ? + otp ~135c pnp ltm4639 4639f
10 for more information www.linear.com/ltm4639 decoupling requirements symbol parameter conditions min typ max units c in external input capacitor requirement (v in = 2.375 v to 7v, v out = 1.5 v ), c pwr 4.5 v i out = 20a, 4 22f ceramic x7r capacitors (see table 5) 88 f c out external output capacitor requirement (v in = 2.375 v to 7v, v out = 1.5 v), c pwr 4.5 v i out = 20a (see table 5) 400 f t a = 25c. use figure 1 configuration . power module description the ltm4639 is a low input voltage,high performance single output standalone nonisolated switching mode dc/ dc power supply. it can provide a 20 a output with few external input and output capacitors. this module provides precisely regulated output voltages programmable via external resistors from 0.6v dc to 5.5v dc over a 2.375v to 7 v input range. the typical application schematic is shown in figure 22. the ltm4639 has an integrated constant- frequency current mode regulator, power mosfets , 0.3 h inductor, and other supporting discrete components. the switching frequency range is from 250 khz to 770 khz, and the typical operating frequency is shown in table 5 for each v out . for switching noise-sensitive applications, it can be externally synchronized from 250 khz to 800 khz, subject to minimum on-time limitations. a single resistor is used to program the frequency. see the applications information section. with current mode control and internal feedback loop compensation, the ltm4639 module has sufficient stability margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. current mode control provides cycle-by-cycle fast current limit in an overcurrent condition. an internal overvoltage monitor protects the output voltage in the event of an overvoltage >10%. the top mosfet is turned off and the bottom mosfet is turned on until the output is cleared. overtemperature protection will turn off the regulators run pin at ~130 c to 137 c . see applications information . operation pulling the run pin below 1.1 v forces the regulator into a shutdown state. the track/ss pin is used for programming the output voltage ramp and voltage tracking during start-up. see the application information section. the ltm4639 is internally compensated to be stable over all operating conditions with compa tied to compb. table 5 provides a guideline for input and output capacitances for several operating conditions. ltpowercad? is available for transient and stability analysis. custom compensation can be used with the compa pin using the ltpowercad and an external compensation network. the v fb pin is used to program the output voltage with a single external resistor to ground. a remote sense amplifier is provided for accurately sensing output voltages 3.3v at the load point. multiphase operation can be easily employed with the synchronization inputs using an external clock source. see application examples. high efficiency at light loads can be accomplished with selectable burst mode operation using the mode_pllin pin. these light load features will accommodate battery operation. efficiency graphs are provided for light load operation in the typical performance characteristics section. a temp + and temp C pin is provided to allow the internal device temperature to be monitored using an onboard diode connected pnp transistor. this diode connected pnp transistor can be used with temp monitor devices like the ltc2990, ltc2997, ltc2974 and ltc2978. ltm4639 4639f
11 for more information www.linear.com/ltm4639 applications information the typical ltm4639 application circuit is shown in fig- ure 22. external component selection is primarily determined by the maximum load current and output voltage. refer to table 5 for specific external capacitor requirements for particular applications. v in to v out step-down ratios there are restrictions in the v in to v out step-down ratio that can be achieved for a given input voltage. the duty cycle is 94% typical at 500 khz operation. the v in to v out minimum dropout is a function of load current and operation at very low input voltage and high duty cycle applications. at very low duty cycles the minimum 100 ns on-time must be maintained. see the frequency adjustment section and temperature derating curves. output voltage programming the pwm controller has an internal 0.6v 1% reference voltage. as shown in the block diagram, a 60.4 k internal feedback resistor connects the v out_lcl and v fb pins together. when the remote sense amplifier is used, then diff_out is connected to the v out_lcl pin. if the remote sense amplifier is not used, then v out_lcl connects to v out . the output voltage will default to 0.6 v with no feedback resistor. adding a resistor r fb from v fb to ground programs the output voltage: v out = 0.6v ? 60.4k + r fb r fb table 1. v fb resistor table vs various output voltages v out (v) 0.6 1.0 1.2 1.5 1.8 2.5 3.3 5.0 r fb (k) open 90.9 60.4 40.2 30.1 19.1 13.3 8.25 for parallel operation of n ltm4639s , the following equation can be used to solve for r fb : r fb = 60.4k / n v out 0.6v C 1 tie the v fb pins together for each parallel output. the comp pins must be tied together also. input capacitors the ltm4639 module should be connected to a low ac- impedance dc source. additional input capacitors are needed for the rms input ripple current rating. the i cin ( rms ) equation which follows can be used to calculate the input capacitor requirement. typically 22 f x7r ceramics are a good choice with rms ripple current ratings of ~ 2 a each. a 47 f to 100 f surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. this bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. if low impedance power planes are used, then this bulk capacitor is not needed. for a buck converter, the switching duty cycle can be estimated as: d = v out v in without considering the inductor ripple current, for each output the rms current of the input capacitor can be estimated as: i cin(rms) = i out(max) % ? d ?(1Cd) where % is the estimated efficiency of the power module. the bulk capacitor can be a switcher-rated aluminum electrolytic capacitor or a polymer capacitor. output capacitors the ltm4639 is designed for low output voltage ripple noise. the bulk output capacitors defined as c out are chosen with low enough effective series resistance (esr) to meet the output voltage ripple and transient requirements. c out can be a low esr tantalum capacitor, low esr polymer capacitor or ceramic capacitors. the typical output capacitance range is from 200 f to 800f. additional output filtering may be required by the system designer if further reduction of output ripple or dynamic transient spikes is required. table 5 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 10a/s transient. the table optimizes total equivalent esr and total bulk capacitance to optimize the transient performance. ltm4639 4639f
12 for more information www.linear.com/ltm4639 stability criteria are considered in the table 5 matrix, and ltpowercad is available for stability analysis and custom compensation for loop optimization using the compa pin. multiphase operation will reduce effective output ripple as a function of the number of phases. application note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. ltpowercad can be used to calculate the output ripple reduction as the number of implemented phases increase by n times. burst mode operation the ltm4639 is capable of burst mode operation in which the power mosfets operate intermittently based on load demand, thus saving quiescent current. for applications where maximizing the efficiency at very light loads is a high priority, burst mode operation should be applied. to enable burst mode operation, simply float the mode_ pllin pin. during burst mode operation, the peak current of the inductor is set to approximately 30% of the maximum peak current value in normal operation even though the voltage at the compa pin indicates a lower value. the voltage at the compa pin drops when the inductors average current is greater than the load requirement. as the comp a voltage drops below 0.5 v, the burst comparator trips, causing the internal sleep line to go high and turn off both power mosfets. in sleep mode, the internal circuitry is partially turned off, reducing the quiescent current. the load current is now being supplied from the output capacitors. when the output voltage drops, causing compa to rise, the internal sleep line goes low, and the ltm4639 resumes normal operation. the next oscillator cycle will turn on the top power mosfet and the switching cycle repeats. pulse-skipping mode operation in applications where low output ripple and high effi- ciency at intermediate currents are desired, pulse - skipping mode should be used. pulse-skipping operation allows the ltm4639 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. tying the mode_pllin pin to intv cc enables pulse-skipping operation. with pulse-skipping mode at light load, the internal current comparator may remain tripped for several cycles, thus skipping operation cycles. this mode has lower ripple than burst mode operation and maintains a higher frequency operation than burst mode operation. forced continuous operation in applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. forced continuous operation can be enabled by tying the mode_pllin pin to ground. in this mode, inductor current is allowed to reverse during low output loads, the compa voltage is in control of the current comparator threshold throughout, and the top mosfet always turns on with each oscillator pulse. during start- up, forced continuous mode is disabled and inductor current is prevented from reversing until the ltm4639s output voltage is in regulation. multiphase operation for outputs that demand more than 20 a of load current, multiple ltm4639 devices can be paralleled to provide more output current without increasing input and output ripple voltage. the mode_pllin pin allows the ltm4639 to be synchronized to an external clock and the internal phase-locked loop allows the ltm4639 to lock onto input clock phase as well. the f set resistor is selected for normal frequency, then the incoming clock can synchronize the device over the specified range. see figure 24 for a synchronizing example circuit. a multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. the rms input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used ( assuming that the input voltage is greater than the number of phases used times the output voltage). the output ripple amplitude is also reduced by the number of phases used. see application note 77. the ltm4639 device is an inherently current mode controlled device, so parallel modules will have good current sharing. this will balance the thermals in the design. tie the compa and v fb pins of each ltm4639 applications information ltm4639 4639f
13 for more information www.linear.com/ltm4639 together to share the current evenly. figure 24 shows a schematic of the parallel design. input rms ripple current cancellation application note 77 provides a detailed explanation of multiphase operation. the input rms ripple current cancellation mathematical derivations are presented, and a graph is displayed representing the rms ripple current reduction as a function of the number of interleaved phases (see figure 2). pll, frequency adjustment and synchronization the ltm4639 switching frequency is set by a resistor ( r fset ) from the f set pin to signal ground. a 10 a current (i freq ) flowing out of the f set pin through r fset develops a voltage on f set . r fset can be calculated as: r fset = freq 500khz / v + 0.2v ? ? ? ? ? ? 1 10a applications information figure 3. relationship between switching frequency and voltage at the f set pin figure 2. normalized input rms ripple current vs duty cycle for one to six module regulators (phases) 0.75 0.8 4639 f02 0.70.650.60.550.50.450.40.350.30.250.20.150.1 0.85 0.9 duty cycle (v out /v in ) 0 dc load current rms input ripple current 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 1 phase 2 phase 3 phase 4 phase 6 phase f set pin voltage (v) 0 switching frequency (khz) 0.5 1 1.5 2 4639 f03 2.5 0 100 300 400 500 900 800 700 200 600 the relationship of f set voltage to switching frequency is shown in figure 3. for low output voltages from 0.6 v to 1.2v, 300 khz operation is an optimal frequency for the best power conversion efficiency while maintaining the inductor current to about 40% to 50% of maximum load current. for output voltages from 1.5 v to 1.8v, 450khz is optimal. for output voltages from 2.5 v to 5v, 600khz ltm4639 4639f
14 for more information www.linear.com/ltm4639 applications information is optimal. see efficiency graphs for optimal frequency set point. the ltm4639 can be synchronized from 250khz to 800khz with an input clock that has a high level above 2v and a low level below 0.8 v. see the typical applications section for synchronization examples. the ltm4639 minimum on-time is limited to approximately 100ns. guardband the on-time to 110 ns. the on-time can be calculated as: t on(min) = 1 freq ? v out v in ? ? ? ? ? ? output voltage tracking output voltage tracking can be programmed externally using the track/ss pin. the output can be tracked up and down with another regulator. the master regulators output is divided down with an external resistor divider that is the same as the slave regulators feedback divider to implement coincident tracking. the ltm4639 uses an accurate 60.4 k resistor internally for the top feedback resistor. figure 4 shows an example of coincident tracking. v out(slave) = 1 + 60.4k r ta ? ? ? ? ? ? ? v track figure 4. dual outputs (1.5v and 1.2v) with tracking pgood v out v out_lcl diff_out v osns + v osns ? v fb ltm4639 v in compa compb track/ss run f set mode_pllin temp ? temp + 14f r2 5k r fb1 40.2k r4 100k 180pf 2.2f c ss soft-start capacitor v out2 1.5v 20a c8 680f 2.5v 2 c11 100f 6.3v 2 c in1 22f 16v 4 intv cc extv cc v in 3.3v sgnd gnd ot_test + pgood v out v out_lcl diff_out v osns + v osns ? v fb ltm4639 c pwr v in intv cc extv cc c pwr r1 5k r fb 60.4k 180pf 22pf 22pf v out1 1.2v 20a c4 680f 2.5v 2 c6 100f 6.3v 2 4639 f04 + r tb 60.4k r ta 60.4k master ramp or output v in 3.3v c in2 22f 16v 4 r3 100k +5v bias +5v bias 2.2f sgnd gnd ot_test compa compb track/ss run f set mode_pllin temp ? temp + 180pf 180pf ltm4639 4639f
15 for more information www.linear.com/ltm4639 applications information figure 5. output voltage coincident tracking characteristics 4639 f05 time slave output master output output voltage where mr is the masters output slew rate and sr is the slaves output slew rate in volts/time. when coincident tracking is desired, then mr and sr are equal, thus r tb is equal to 60.4k. r ta is derived from equation: r ta = 0.6v v fb 60.4k + v fb r fb C v track r tb where v fb is the feedback voltage reference of the regulator , and v track is 0.6 v. since r tb is equal to the 60.4 k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then r ta is equal to r fb with v fb = v track . therefore r tb = 60.4 k, and r ta = 60.4 k in figure 4. in ratiometric tracking, a different slew rate maybe desired for the slave regulator. r tb can be solved for when sr is slower than mr. make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach its final value before the master output. for example, mr = 1.5 v/ms, and sr = 1.2 v/ms. then r tb = 75k. solve for r ta to equal 51.1k. for applications that do not require tracking or sequencing, simply tie the track/ss pin to intv cc to let run control the turn on/off. when the run pin is below its threshold or the v in undervoltage lockout, then track/ss is pulled low. overcurrent and overvoltage protection the ltm4639 has overcurrent protection ( ocp) in a short circuit. the internal current comparator threshold folds back during a short to reduce the output current. an over voltage condition ( ovp) above 10% of the regulated output voltage will force the top mosfet off and the bottom mosfet on until the condition is cleared. foldback current limiting is disabled during soft-start or tracking start-up. v track is the track ramp applied to the slaves track pin. v track has a control range of 0 v to 0.6 v, or the internal reference voltage. when the masters output is divided down with the same resistor values used to set the slaves output, then the slave will coincident track with the master until it reaches its final value. the master will continue to its final value from the slaves regulation point ( see figure 5). voltage tracking is disabled when v track is more than 0.6 v. r ta in figure 4 will be equal to r fb for coincident tracking. the track/ss pin of the master can be controlled by an external ramp or the soft- start function of that regulator can be used to develop that master ramp. the ltm4639 can be used as a master by setting the ramp rate on its track pin using a soft-start capacitor. a 1.2 a current source is used to charge the soft-start capacitor. the following equation can be used: t soft-start = 0.6v ? c ss 1.2a ? ? ? ? ? ? ratiometric tracking can be achieved by a few simple calculations and the slew rate value applied to the master s track/ss pin. as mentioned above, the track/ss pin has a control range from 0 v to 0.6 v. the masters track/ss pin slew rate is directly equal to the masters output slew rate in volts/time. the equation: mr sr ? 60.4k = r tb ltm4639 4639f
16 for more information www.linear.com/ltm4639 temperature monitoring measuring the absolute temperature of a diode is possible due to the relationship between current, voltage and temperature described by the classic diode equation: i d = i s ? e v d ? v t ? ? ? ? ? ? or v d = ? v t ? ln i d i s where i d is the diode current, v d is the diode voltage, is the ideality factor ( typically close to 1.0) and i s (saturation current) is a process dependent parameter. v t can be broken out to: v t = k ? t q where t is the diode junction temperature in kelvin, q is the electron charge and k is boltzmanns constant. v t is approximately 26 mv at room temperature (298 k) and scales linearly with kelvin temperature. it is this linear temperature relationship that makes diodes suitable applications information temperature sensors. the i s term in the equation above is the extrapolated current through a diode junction when the diode has zero volts across the terminals. the i s term varies from process to process, varies with temperature, and by definition must always be less than i d . combining all of the constants into one term: k d = ? k q where k d = 8.62 ?5 , and knowing ln (i d /i s ) is always positive because i d is always greater than i s , leaves us with the equation that: v d = t(kelvin) ? k d ? ln i d i s where v d appears to increase with temperature. it is common knowledge that a silicon diode biased with a current source has an approximate C2 mv/c temperature relationship (figure 6), which is at odds with the equation. in fact, the i s term increases with temperature, reducing the ln(i d /i s ) absolute value yielding an approximate C2mv/c composite diode voltage slope. figure 6. diode voltage v d vs temperature t(c) for different bias currents 4639 f06 temperature (c) ?173 ?73 27 127 diode voltage (v) 0.4 0.6 0.8 1.0 ?v d i d = 100a i d = 10a ltm4639 4639f
17 for more information www.linear.com/ltm4639 to obtain a linear voltage proportional to temperature, we cancel the i s variable in the natural logarithm term to remove the i s dependency from the following equation. this is accomplished by measuring the diode voltage at two currents i 1 , and i 2 , where i 1 = 10???i 2 subtracting we get: ?v d = t(kelvin) ? k d ?in i 1 i s ? t(kelvin) ? k d ?in i 2 i s combining like terms, then simplifying the natural log terms yields: ? v d = t(kelvin) ? k d ? in(10) and redefining constant k d = k d ? in(10) = 198v/k yields ? v d = k d ? t(kelvin) solving for temperature: t(kelvin) = ?v d k' d , t(kelvin) = [ c] + 273.15, [ c] = t(kelvin) ? 273.15 means that is we take the difference in voltage across the diode measured at two currents with a ratio of 10, the resulting voltage is 198 v per kelvin of the junction with a zero intercept at 0 kelvin. the diode connected pnp transistor at the temp + , temp C pins can be used to monitor the internal temperature of the ltm4639. a general temperature monitor can be implemented by connecting a resistor between temp + and v in to set the current to 100 a, grounding the temp C pin, and then monitoring the diode voltage drop with temperature. a more accurate temperature monitor can be achieved with a circuit injecting two currents that are at a 10:1 ratio. see figure 22 for an example. overtemperature protection the internal overtemperature protection monitors the internal temperature of the module and shuts off the regulator at ~130 c to 137 c. once the regulator cools down the regulator will restart. run enable the run pin is used to enable the power module or sequence the power module. the threshold is 1.25 v, and the pin has an internal 5.1 v zener to protect the pin. the run pin can be used as an undervoltage lockout (uvlo) function by connecting a resistor divider from the input supply to the run pin: v uvlo = ((r1+r2)/r2) ? 1.25v see figure 1, simplified block diagram. intv cc regulator the ltm4639 has an internal low dropout regulator from v in called intv cc . this regulator output has a 2.2 f ceramic capacitor internal. an additional 2.2 f ceramic capacitor is needed on this pin to ground. this regulator powers the internal controller and mosfet drivers. the gate driver current is ~20 ma for 750 khz operation. the regulator loss can be calculated as: ( v in C 5v) ? 20ma = p loss extv cc external voltage source 4.7 v can be applied to this pin to eliminate the internal intv cc ldo power loss and increase regulator efficiency. a 5 v supply can be applied to run the internal circuitry and power mosfet driver. if unused, leave pin floating. extv cc must be less than v in at all times during power-on and power-off sequences. stability compensation the ltm4639 has already been internally compensated for all output voltages. table 5 is provided for most application requirements. ltpowercad is available for other control loop optimization. thermal considerations and output current derating the thermal resistances reported in the pin configuration section of the data sheet are consistent with those parameters defined by jesd51-12 and are intended for use with finite element analysis ( fea) software modeling tools that leverage the outcome of thermal modeling, simulation , and correlation to hardware evaluation performed on a module package mounted to a hardware test board. the motivation for providing these thermal coefficients in found in jesd 51-12 ( guidelines for reporting and using electronic package thermal information). applications information ltm4639 4639f
18 for more information www.linear.com/ltm4639 applications information many designers may opt to use laboratory equipment a nd a test vehicle such as the demo board to predict the module regulators thermal performance in their application at various electrical and environmental operating conditions to compliment any fea activities. without fea software, the thermal resistances reported in the pin configuration section are, in and of themselves, not relevant to providing guidance of thermal performance; instead, the derating curves provided in this data sheet can be used in a manner that yields insight and guidance pertaining to ones application-usage, and can be adapted to correlate thermal performance to ones own application. the pin configuration section gives four thermal coefficients explicitly defined in jesd51-12; these coefficients are quoted or paraphrased below: 1 ja , the thermal resistance from junction to ambient, is the natural convection junction- to- ambient air thermal resistance measured in a one cubic foot sealed enclosure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a 95mm 76mm pcb with four layers. 2 jcbottom , the thermal resistance from junction to the bottom of the product case , is determined with all of the component power dissipation flowing through the bottom of the package. in the typical module regulator, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. as a result, this thermal resistance value may be useful for comparing packages but the test conditions dont generally match the users application. 3 jctop , the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part . as in the case of jcbottom , this value may be useful for comparing packages but the test conditions dont generally match the users application. 4 jb , the thermal resistance from junction to the printed circuit board, is the junction- to- board thermal resistance where almost all of the heat flows through the bottom of the module package and into the board, and is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and a portion of the board. the board temperature is measured a specified distance from the package. a graphical representation of the aforementioned thermal resistances is given in figure 7; blue resistances are contained within the module regulator, whereas green resistances are external to the module package. as a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by jesd51-12 or provided in the pin configuration section replicates or conveys normal operating conditions of a module regulator. for example, in normal board-mounted applications, never does 100% of the devices total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the module packageas the standard defines for jctop and jcbottom , respectively. in practice, power loss is thermally dissipated in both directions away from the packagegranted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. within the ltm4639, be aware there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. to reconcile this complication without sacrificing modeling simplicitybut also not ignoring practical realitiesan approach has been taken using fea software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet : (1) initially, fea software is used to accurately build the mechanical geometry of the ltm4639 and the specified pcb with all of the correct material coefficients along with accurate power loss source definitions ; (2) this model simulates a software - defined jedec environment consistent with jesd51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the ltm4639 4639f
19 for more information www.linear.com/ltm4639 applications information jedec-defined thermal resistance values ; (3) the model and fea software is used to evaluate the ltm4639 with heat sink and airflow ; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled- environment chamber while operating the device at the same power loss as that which was simulated. the outcome of this process and due diligence yields the set of derating curves shown in this data sheet. the 1 v , 2.5 v and 5 v power loss curves in figures 8 to 10 can be used in coordination with the load current derating curves in figures 11 to 20 for calculating an approximate ja thermal resistance for the ltm 463 9 with various heat sinking and airflow conditions . the power loss curves are taken at room temperature and are increased with a multiplicative factor according to the junction temperature , which is 1.4 for 120 c. the derating curves are plotted with the output current starting at 20a and the ambient temperature at ~40 c. the output voltages are 1v , 2.5 v and 5 v. these are chosen to include the lower , middle and higher output voltage ranges for correlating the t hermal r esistance . thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis . the junction temperatures are monitored while ambient temperature is increased with and without airflow . the p ower lo ss increase with ambient temperature change is factored into the derating curves . the junctions are maintained at ~120 c maximum while lowering output current or power with increasing ambient temperature . the decreased output current will decrease the internal module loss as ambient temperature is increased . the monitored junction temperature of 120 c minus the ambient operating temperature specifies how much module temperature rise can be allowed , as an example , in figure 13 the load current is derated to ~17 a at ~80 c with no air or heat sink and the power loss for the 7 v to 1.0 v at 17 a output is about 4.2 w. the 4.2 w loss is calculated with the ~3 w room figure 7. graphical representation of jesd51-12 thermal coefficients 4639 f07 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient thermal resistance components case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance ltm4639 4639f
20 for more information www.linear.com/ltm4639 figure 8. 3.3v input power loss curves figure 9. 5v input power loss curves applications information figure 10. 7v input power loss curves temperature loss from the 7 v to 1.0 v power loss curve at 17 a, and the 1.4 multiplying factor at 120 c junction . if the 80 c ambient temperature is subtracted from the 120 c junction temperature , then the difference of 40 c divided by 4.2 w equals a 9.5 c/w ja thermal resistance . table 2 specifies a 10 c/w value which is very close. table 2 through table 4 provides equivalent thermal resistances for 1.0 v , 2.5 v and 5 v outputs with and without airflow and heat sinking . the derived thermal resistances in tables 2 thru 4 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient , thus maximum junction temperature . room temperature power loss can be derived from the efficiency curves in the typical performance characteristics section and adjusted with the above ambient temperature multiplicative factors . the printed circuit board is a 1.6 mm thick four layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers . the pcb dimensions are 95 mm 76 mm . the bga heat sinks are listed in ta ble 6. output current (a) 0 power loss (w) 2.5 3.0 3.5 20 4639 f08 2.0 1.5 0 2 4 6 8 10 18161412 1.0 0.5 5.0 4.5 4.0 3.3v to 1.8v power loss 3.3v to 1.5v power loss 3.3v to 1.2v power loss 3.3v to 1v power loss output current (a) 0 efficiency (%) 2.5 3.0 3.5 20 4639 f09 2.0 1.5 0 2 4 6 8 10 18161412 1.0 0.5 5.0 4.5 4.0 5v to 3.3v power loss 5v to 2.5v power loss 5v to 1.8v power loss 5v to 1.5v power loss 5v to 1.2v power loss 5v to 1v power loss output current (a) 0 efficiency (%) 2.5 3.0 3.5 20 4639 f10 2.0 1.5 0 2 4 6 8 10 18161412 1.0 0.5 5.0 4.5 4.0 7v to 5v power loss 7v to 3.3v power loss 7v to 2.5v power loss 7v to 1.8v power loss 7v to 1.5v power loss 7v to 1.2v power loss 7v to 1v power loss figure 11. 5v in to 1.0v out no heat sink figure 13. 7v in to 1.0v out no heat sink figure 12. 5v in to 1.0v out with heat sink temperature (c) 0 0 output current (a) 5 15 20 25 40 80 120 4639 f11 10 20 60 100 0 lfm 200 lfm 400 lfm temperature (c) 0 0 output current (a) 5 15 20 25 40 80 140 4639 f13 10 20 60 100 120 0 lfm 200 lfm 400 lfm temperature (c) 0 0 output current (a) 5 15 20 25 40 80 140 4639 f12 10 20 60 100 120 0 lfm 200 lfm 400 lfm ltm4639 4639f
21 for more information www.linear.com/ltm4639 figure 14. 7v in to 1.0v out with heat sink figure 15. 5v in to 2.5v out no heat sink applications information figure 16. 5v in to 2.5v out with heat sink figure 17. 7v in to 2.5v out no heat sink figure 18. 7v in to 2.5v out with heat sink temperature (c) 0 0 output current (a) 5 15 20 25 40 80 140 4639 f14 10 20 60 100 120 0 lfm 200 lfm 400 lfm temperature (c) 0 0 output current (a) 5 15 20 25 40 80 140 4639 f15 10 20 60 100 120 0 lfm 200 lfm 400 lfm temperature (c) 0 0 output current (a) 5 15 20 25 40 80 140 4639 f16 10 20 60 100 120 0 lfm 200 lfm 400 lfm temperature (c) 0 0 output current (a) 5 15 20 25 40 80 140 4639 f17 10 20 60 100 120 0 lfm 200 lfm 400 lfm temperature (c) 0 0 output current (a) 5 15 20 25 40 80 140 4639 f18 10 20 60 100 120 0 lfm 200 lfm 400 lfm figure 19. 7v in to 5v out no heat sink, extv cc = 5v, c pwr = 7v figure 20. 7v in to 5v out with heat sink, extv cc = 5v, c pwr = 7v temperature (c) 0 0 output current (a) 5 15 20 25 40 80 140 4639 f19 10 20 60 100 120 0 lfm 200 lfm 400 lfm temperature (c) 0 0 output current (a) 5 15 20 25 40 80 140 4639 f20 10 20 60 100 120 0 lfm 200 lfm 400 lfm ltm4639 4639f
22 for more information www.linear.com/ltm4639 table 2. 1 v output derating curve v in power loss curve airflow ( lfm ) heat sink ja ( c/w) figures 11, 13 5v, 7v figure 8 0 none 10 figures 11, 13 5v, 7v figure 8 200 none 8 figures 11, 13 5v, 7v figure 8 400 none 7 figures 12, 14 5v, 7v figure 8 0 bga heat sink 9 figures 12, 14 5v, 7v figure 8 200 bga heat sink 6.5 figures 12, 14 5v, 7v figure 8 400 bga heat sink 5.5 table 3. 2.5 v output derating curve v in power loss curve airflow ( lfm ) heat sink ja ( c/w) figures 15, 17 5v, 7v figure 9 0 none 12 figures 15, 17 5v, 7v figure 9 200 none 11 figures 15, 17 5v, 7v figure 9 400 none 10 figures 16, 18 5v, 7v figure 9 0 bga heat sink 10.5 figures 16, 18 5v, 7v figure 9 200 bga heat sink 9.5 figures 16, 18 5v, 7v figure 9 400 bga heat sink 8 table 4. 5v output (5 v output connected to extv cc pin ) derating curve v in power loss curve airflow ( lfm ) heat sink ja ( c/w) figures 19 7v figure 10 0 none 12 figures 19 7v figure 10 200 none 11 figures 19 7v figure 10 400 none 10 figures 20 7v figure 10 0 bga heat sink 10.5 figures 20 7v figure 10 200 bga heat sink 8 figures 20 7v figure 10 400 bga heat sink 7 applications information ltm4639 4639f
23 for more information www.linear.com/ltm4639 applications information c out1 and c out2 ceramic vendors v alue pa rt number tdk 22f, 6.3v c3216x7s0j226m murata 22f, 10v grm31cr61c226ke15l murata 47f, 10v grm31cr61a476ke15l tdk 100f, 6.3v c4532x5r0j107mz murata 100f, 6.3v grm32er60j107m avx 100f, 6.3v 18126d107 mat c out1 and c out2 bulk vendors value part number sanyo poscap 680f, 2.5v 2r5tpf680m6l panasonic 220f, 4v eefcxog221er sanyo poscap 150f, 10v 10tbf150m c in bulk vendor value part number sanyo 100f, 16v 16svp100m table 5*. output voltage response vs component matrix (refer to figure 22). typical measured values standard internal compensation compa and compb tied together v out (v) c in (ceramic) c in (bulk) * c out1 (ceramic) c out2 ( ceramic and bulk ) c ff (pf) c bot (pf) c compa (pf) v in (v) droop (mv) peak-to- peak devia tion (mv) recover y time (s) load step (a/s) r fb (k) freq (khz) track v in 2.5v, 3.3v,5v,7v 1 22f 4 100f 100f 2 680f 2 180 22 180 2.5, 3.3, 5, 7 34 72 34 7.5 90.9 350, 400, 500, 500 1.2 22 f 4 100f 100f 2 680f 2 180 22 180 2.5, 3.3, 5, 7 37 72 34 7.5 60.4 350, 400, 500, 500 1.5 22 f 4 100f 100f 2 680f 2 180 22 180 2.5, 3.3, 5, 7 37 80 34 7.5 40.2 350, 400, 500, 500 1.8 22 f 4 100f 100f 2 680f 2 180 22 180 2.5, 3.3, 5, 7 38 80 34 7.5 30.1 350, 400, 500, 500 2.5 22 f 4 100f 47f 220f - 22 180 3.3, 5, 7 111 225 24 7.5 19.1 400, 500, 550 3.3 22 f 4 100f 22f 150f - 22 180 5,7 150 300 24 7.5 13.3 500, 550 5 22f 4 100f 22f 150f - 22 180 7 187 370 24 7.5 8.25 550 * bulk capacitance is optional if v in has very low input impedance. additional bulk capacitance may be required for 3.3v input depends on source impedance ltm4639 4639f
24 for more information www.linear.com/ltm4639 applications information table 7. recommended heat sinks heat sink manufacturer part number website aavid thermalloy 375424 b 00034 g www . aavidthermalloy . com cool innovations 4-050503 p to 4-050508 p www . coolinnovations . com c out1 and c out2 ceramic vendors v alue pa rt number murata 220f, 4v grm31cr60g227m murata 47f, 10v grm31cr61a476ke15l ltpowercad can be used to optimize the control loop response. examples are shown using ceramic only for high performance transient response v out (v) c in (ceramic) c in (bulk) * c out1 (cer) c out2 ( cer & bulk) c ff (pf) c bot (pf) r s (k) c s (pf) c p (pf) v in (v) droop (mv) peak-to- peak devia tion (mv) rec. time (s) load step (a/s) r fb (k) freq (khz) track v in 2.5v, 3.3v,5v,7v 1 22f 4 100f 200f 6 - 68 22 20 1200 100 2.5, 3.3, 5, 7 40 80 24 7.5 90.9 350, 400, 500, 500 1.2 22 f 4 100f 200f 6 - 68 22 20 1200 100 2.5, 3.3, 5, 7 43 88 24 7.5 60.4 350, 400, 500, 500 1.5 22 f 4 100f 200f 4 - 68 22 20 1200 100 2.5, 3.3, 5, 7 60 122 24 7.5 40.2 350, 400, 500, 500 1.8 22 f 4 100f 200f 4 - 68 22 20 1200 100 2.5, 3.3, 5, 7 64 130 28 7.5 30.1 350, 400, 500, 500 2.5 22 f 4 100f 47f 2 - 47 22 4 4700 47 3.3, 5, 7 179 320 33 5 19.1 400, 500, 550 3.3 22 f 4 100f 47f 2 - 47 22 4 4700 47 5,7 219 400 33 5 13.3 500, 550 5 22f 4 100f 47f 2 - - 22 4 4700 47 7 250 500 24 5 8.25 550 * bulk capacitance is optional if v in has very low input impedance. additional bulk capacitance may be required for 3.3v input depends on source impedance table 6*. output voltage response vs component matrix (refer to figure 22). typical measured values ltm4639 4639f
25 for more information www.linear.com/ltm4639 safety considerations the ltm 4639 does not provide galvanic isolation from v in to v out . there is no internal fuse . if required , a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure . the fuse or circuit breaker should be selected to limit the current to the regulator during overvoltage in case of an internal top mosfet fault. if the internal top mosfet fails, then turning it off will not resolve the overvoltage, thus the internal bottom mosfet will turn on indefinitely trying to protect the load. under this fault condition, the input voltage will source very large currents to ground through the failed internal top mosfet and enabled internal bottom mosfet. this can cause excessive heat and board damage depending on how much power the input voltage can deliver to this system. a fuse or circuit breaker can be used as a secondary fault protector in this situation. the ltm 4639 does support overvoltage protection , overcurrent protection and overtemperature protection . layout checklist/example the high integration of the ltm 4639 makes the pcb board layout very simple and easy . however , to optimize its electrical and thermal performance , some layout c on siderations are still necessary . ? use l arge pcb copper areas for high current paths , including v in , gnd and v out . it helps to minimize the pcb conduction loss and thermal stress . ? plac e high frequency ceramic input and output capacitors next to the v in , gnd and v out pins to minimize high frequency noise . ? plac e a dedicated power ground layer underneath the unit . ? to mini mize the via conduction loss and reduce module thermal stress , use multiple vias for interconnection between top layer and other power layers . ? do not pu t vias directly on the pad , unless they are capped or plated over . ? place test points on signal pins for testing. ? use a separated sgnd ground copper area for components connected to signal pins . connect the sgnd to gnd underneath the unit . ? for p arallel modules , tie the comp and v fb pins together . use an internal layer to closely connect these pins together . figure 21 gives a good example of the recommended layout . applications information figure 21. recommended pcb layout pgnd v in control 4639 f21 control control c1 a1 signal ground v out v out c out c out c in c in compa temp + temp ? c pwr ot_test compb ltm4639 4639f
26 for more information www.linear.com/ltm4639 typical applications figure 22. 2.375 v to 7v in , 1.5 v at 20 a design pgood v out v out_lcl diff_out v osns + v osns ? v fb ltm4639 r1 10k r fb * 40.2k r3 100k 470pf c in 22f 25v 4 c ff * 180pf 2.2f c7 0.1f 680f 2.5v 2 100f 6.3v 2 v out 1.5v 20a c out1 * c out2 * intv cc continuous mode *see table 5 4639 f22 v in 2.375v to 7v + v cc 1.8v d + d ? v ref v ptat ltc2997 v in compa compb track/ss run f set mode_pllin temp ? temp + 1f intv cc extv cc sgnd gnd ot_test c pwr +5v bias v cc gnd 0.1f intv cc 4mv/k 180pf* c30* 22pf ltm4639 4639f
27 for more information www.linear.com/ltm4639 figure 23. 1 v at 40 a, two parallel outputs with 2- phase operation , 350 khz typical applications pgood v out v out_lcl diff_out v osns + v osns ? v fb ltm4639 r fb1 45.3k r2 10k v in 2.375v to 7v c10 22f 16v c7 22f 16v r1 287k 350khz c13 0.1f c8 680f 2.5v 2 c11 100f 6.3v 2 c9 22f 16v intv cc clock sync 0 phase clock sync 180 phase 2.2f c14 1f + pgood v out v out_lcl diff_out v osns + v osns ? v fb ltm4639 c2 22f 16v c3 22f 16v c4 680f 2.5v 2 c6 100f 6.3v 2 c1 22f 16v 4639 f23 + 22pf 1f out1 out2 mod v + gnd set ltc6908-1 1v 40a 75k 75k 180pf intv cc v in compa compb track/ss run f set mode_pllin temp ? temp + 1f intv cc extv cc sgnd gnd ot_test c pwr +5v bias v in compa compb track/ss run f set mode_pllin temp ? temp + intv cc extv cc sgnd gnd ot_test c pwr +5v bias 220f 10v + 180pf 2.2f ltm4639 4639f
28 for more information www.linear.com/ltm4639 typical applications figure 24. 1.2 v, 80a, current sharing with 4- phase operation pgood v out v out_lcl diff_out v osns + v osns ? v fb ltm4639 r fb2 15k r1 10k c22 22f 16v r2 143k 4-phase clock c28 0.22f 470pf v in 3.3v to 7v v out 1.2v at 80a c21 680f 2.5v 2 c15 680f 2.5v 2 c18 100f 6.3v 2 c8 680f 2.5v 2 c11 100f 6.3v 2 c4 680f 2.5v 2 c6 100f 6.3v 2 c24 100f 6.3v 2 c20 22f 16v c2 1f + pgood v out v out_lcl diff_out v osns + v osns ? v fb ltm4639 intv cc intv cc + v + div ph out1 out2 set mod gnd out4 out3 ltc6902 350khz pgood v out v out_lcl diff_out v osns + v osns ? v fb ltm4639 + pgood v out v out_lcl diff_out v osns + v osns ? v fb ltm4639 4639 f24 + 75k 75k 75k 75k 220f 6.3v c18 22f 16v c14 22f 16v 22f 25v c1 22f 16v c3 22f 16v 22f 25v c9 22f 16v c7 22f 16v 2.2f 2.2f 2.2f v in compa compb track/ss run f set mode_pllin temp ? temp + 2.2f intv cc extv cc sgnd gnd ot_test c pwr +5v bias ot_test ot_test ot_test v in compa compb track/ss run f set mode_pllin temp ? temp + intv cc extv cc sgnd gnd c pwr +5v bias v in compa compb track/ss run f set mode_pllin temp ? temp + intv cc extv cc sgnd gnd c pwr +5v bias v in compa compb track/ss run f set mode_pllin temp ? temp + intv cc extv cc sgnd gnd c pwr +5v bias + 180pf 22pf ltm4639 4639f
29 for more information www.linear.com/ltm4639 pin id function pin id function pin id function pin id function pin id function pin id function a1 v in b1 v in c1 v in d1 gnd e1 gnd f1 gnd a2 v in b2 v in c2 v in d2 gnd e2 gnd f2 gnd a3 v in b3 v in c3 v in d3 gnd e3 gnd f3 gnd a4 v in b4 v in c4 v in d4 gnd e4 gnd f4 gnd a5 v in b5 v in c5 v in d5 gnd e5 gnd f5 gnd a6 v in b6 v in c6 v in d6 gnd e6 temp C f6 temp + a7 intv cc b7 c pwr c7 gnd d7 C e7 gnd f7 gnd a8 mode_pllin b8 C c8 C d8 gnd e8 C f8 gnd a9 track/ss b9 ot_test c9 gnd d9 intv cc e9 gnd f9 gnd a10 run b10 C c10 mtp2 d10 mtp5 e10 C f10 C a11 compa b11 mtp1 c11 mtp3 d11 mtp6 e11 C f11 pgood a12 compb b12 f set c12 mtp4 d12 mtp7 e12 extv cc f12 v fb pin id function pin id function pin id function pin id function pin id function pin id function g1 gnd h1 gnd j1 v out k1 v out l1 v out m1 v out g2 gnd h2 gnd j2 v out k2 v out l2 v out m2 v out g3 gnd h3 gnd j3 v out k3 v out l3 v out m3 v out g4 gnd h4 gnd j4 v out k4 v out l4 v out m4 v out g5 gnd h5 gnd j5 v out k5 v out l5 v out m5 v out g6 gnd h6 gnd j6 v out k6 v out l6 v out m6 v out g7 gnd h7 gnd j7 v out k7 v out l7 v out m7 v out g8 gnd h8 gnd j8 v out k8 v out l8 v out m8 v out g9 gnd h9 gnd j9 v out k9 v out l9 v out m9 v out g10 C h10 C j10 v out k10 v out l10 v out m10 v out g11 sgnd h11 sgnd j11 C k11 v out l11 v out m11 v out g12 pgood h12 sgnd j12 v osns + k12 diff_out l12 v out_lcl m12 v osns C package description pin assignment table (arranged by pin number) package row and column labeling m ay vary among module products. review each package layout carefully. ltm4639 4639f
30 for more information www.linear.com/ltm4639 package photo figure 25. 7v in , 5v at 20a design pgood v out v out_lcl diff_out v osns + v osns ? v fb ltm4639 5k r fb 8.25k 140k 22f 10v 4 v in 7v 0.1f 4639 f25 v in compa compb track/ss run f set mode_pllin temp ? temp + intv cc extv cc sgnd gnd ot_test c pwr 2.2f c compa 180pf 22f 6.3v 150f 6.3v v out 5v 20a + c bot 22pf ltm4639 4639f
31 for more information www.linear.com/ltm4639 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature package top view 4 pin ?a1? corner x y aaa z aaa z package bottom view pin 1 3 see notes suggested pcb layout top view bga 133 1113 rev ? ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? detail a 0.0000 0.0000 detail a ?b (133 places) detail b substrate 0.27 ? 0.37 3.95 ? 4.05 // bbb z d a a1 b1 ccc z detail b package side view mold cap z m x yzddd m zeee 0.630 0.025 ? 133x symbol a a1 a2 b b1 d e e f g aaa bbb ccc ddd eee min 4.72 0.50 4.22 0.60 0.60 nom 4.92 0.60 4.32 0.75 0.63 15.0 15.0 1.27 13.97 13.97 max 5.12 0.70 4.42 0.90 0.66 0.15 0.10 0.20 0.30 0.15 notes dimensions total number of balls: 133 e b e e b a2 f g bga package 133-lead (15mm 15mm 4.92mm) (reference ltc dwg # 05-08-1962 rev ?) 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 fgh m l jk e abcd 2 1 4 3 5 6 7 12 8 9 10 11 5. primary datum -z- is seating plane 6. solder ball composition is 96.5% sn/3.0% ag/0.5% cu 7 package row and column labeling may vary among module products. review each package layout carefully ! 7 see notes bga package 133-lead (15mm 15mm 4.92mm) (reference ltc dwg # 05-08-1962 rev ?) ltm4639 4639f
32 for more information www.linear.com/ltm4639 ? linear technology corporation 2014 lt 0914 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltm4639 related parts design resources typical application part number description comments ltm4637 higher v in range than the ltm4639 4.5v v in 20v, 20a ltm4611 lower v in range than the ltm4639 1.5v v in 5.5v,15a, auxiliary v bias not required ltm4644 quad output, 4a each 2.375v v in 14v, low v in required auxiliary v bias , current share to 16a ltm4615 triple output, 4a, 4a, 1.5a 2.375v v in 5.5v, auxiliary v bias not required ltm4616 dual output, 8a each 2.7v v in 5.5v, current share to 16a, auxiliary v bias not required ltm4608a lower i out and smaller package than the ltm4639 2.7v v in 5.5v, 8a, 9mm 15mm 2.8mm 1.8v at 20a design with input current and temperature monitoring pgood v out v out_lcl diff_out v osns + v osns ? v fb ltm4639 r1 5k r fb 30.1k r3 125k 470pf measure temp c in 22f 25v 4 c7 0.1f c4 220f 6.3v x5r 6 v out 1.8v at 20a continuous mode 4639 ta02 10m c ff 68pf c bot 22pf c p 100pf v in compa compb track/ss run f set mode_pllin temp ? temp + intv cc extv cc sgnd gnd ot_test c pwr +5v input ltc2990 gnd v cc sda scl adr0 v3 v4 adr1 v2v1 0.1f 2-wire i 2 c interface measure i in c s 1200pf r s 20k subject description module design and manufacturing resources design: ? selector guides ? demo boards and gerber files ? free simulation tools manufacturing: ? quick start guide ? pcb design, assembly and manufacturing guidelines ? package and board level reliability module regulator products sear ch 1. sort table of products by parameters and download the result as a spread sheet. 2. search using the quick power search parametric table. techclip videos quick videos detailing how to bench test electrical and thermal performance of module products. digital power system management linear technologys family of digital power supply management ics are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature eeprom for storing user configurations and fault logging. ltm4639 4639f

▲Up To Search▲

Price & Availability of LTM4639-15

	To Download LTM4639-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .